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commercial temperature range idtcv174c programmable flexpc clock for p4 processor 1 may 2006 idtcv174c commercial temperature range programmable flexpc clock for p4 processor sata sm bus controller control logic 48mhz/96mhz output buffer sdata sclk ckprwgd/pd# fsc,b,a 48mhz dot96/src0 fixed pll pll2 xtal osc amp cpu, src, pci output buffer stop logic xtal_in xtal_out cpu[1:0] pll1 ssc n programmable src5_en, lte cr#_[f:a] cpu_stop# pci_stop# itp_en pll3 ssc n programmable src clk output buffer stop logic src[7:1] cpu_itp/src8 ref pci[4:0], pcif5 the idt logo is a registered trademark of integrated device technology, inc. ? 2005 integrated device technology, inc. dsc 6898/8 features: ? compliant with intel ck505 ? power management control suitable for low power applications ? one high precision pll for cpu/src/pci, ssc and n program- ming ? one high precision pll for src/pci, ssc and n programming ? one high precision pll for 96mhz/48mhz ? push-pull ios for differential outputs ? support spread spectrum modulation, ?0.5 down spread and others ? support smbus block read/write, index read/write ? selectable output strength ? smooth transition for n programming ? available in ssop and tssop packages functional block diagram description: idtcv174c is a 56 pin clock device, incorporating intel ck505 requirements for the intel advance p4 processor. the cpu output buffer is designed to support up to 400mhz reference clock for the cpu. this chip has three plls inside for cpu, src/pci and 48mhz/dot96 io clocks. outputs: ? 2*0.7v differential cpu clk pair ? 7*0.7v differential src clk pair ? one cpu_itp/src differential clock pair ? one src0/dot96 differential clock pair ? 6*pci, 33.3mhz ? 1*48mhz ? 1*ref ? 1*sata key specifications: ? cpu/src clk cycle to cycle jitter < 85ps ? pci clk cycle to cycle jitter < 500ps
commercial temperature range 2 idtcv174c programmable flexpc clock for p4 processor pin configuration tssop top view 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 scl sda fsb/test_mode xtal_in xtal_out v dd _ref cpuc0 v ss _cpu cput0 srcc6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 srct3/cr#_c pci0/cr#_a pci3 v ss _pci usb_48/fsa v dd _io srct0/dot96t v ss _48mhz srct1/se1 srcc8/cpu_itpc v dd _pll3 v dd _48mhz v dd _pll3_io ref/fsc/test_sel ckpwrgd/pd# v dd _cpu cpuc1 29 30 31 32 v dd _pci pci1/cr#_b pcif5/itp_en pci4/src5_en v ss _io srcc1/se2 v ss _pll3 satat/srct2 satac/srcc2 v ss _src srcc3/cr#_d v dd _src_io srct4 srcc4 v ss _ref cput1 v dd _cpu_io io_v out srct8/cpu_itpt v dd _src_io srct7/cr#_f srct6 srcc7/cr#_e v ss _src v dd _src pci_stop#/srct5 cpu_stop#/srcc5 pci2//lte srcc0/dot96c
commercial temperature range idtcv174c programmable flexpc clock for p4 processor 3 pin description pin # name type description 1 pci0/cr#_a i/o 33.33mhz/src0, 2 differential clock output enable, control src0 and src2, 0 = enable. mode is selected by smbus control register. default is pci clock mode 2v dd _pci pwr 3.3v 3 pci1/cr#_b i/o 33.33mhz/src1, 2 differential clock output enable, control src1 and src4, 0 = enable. mode is selected by smbus control register. default is pci clock mode 4 pci2/lte i/o 33.33mhz. high = overclocking disabled. power-on latch. 5 pci3 out 33.33mhz 6 pci4/src5_en i/o 33.33mhz. pin 29, 30 mode selection. power on latch, high = src5, low = cpu and pci stop# 7 pcif5/itp_en i/o 33.33mhz. pin 38, 39 mode selection. power on latch, high = cpu_itp, low = src8 8v ss _pci gnd gnd 9v dd _48 pwr 3.3v 10 usb 48/fs_a i/o 48mhz/ frequency select, power on latch 11 v ss _48 gnd gnd 12 v dd _io pwr 0.8v 13 srct0/dot96t out differential output clock. src or dot96. mode selected by smbus control register, default is src0 14 srcc0/dot96c out differential output clock. src or dot96. mode selected by smbus control register, default is src0 15 v ss _io gnd gnd 16 v dd _pll3 pwr 3.3v 17 srct1/se1 out differential or single end clock output. mode selected by smbus control register. default is src1. 18 srcc1/se2 out differential or single end clock output. mode selected by smbus control register. default is src1 19 v ss _pll3 gnd gnd 20 v dd _pll3_io pwr 0.8v 21 srct2/satat out differential output clock 22 srcc2/satac out differential output clock 23 v ss _src gnd gnd 24 srct3/cr#_c i/o src clock/ src differential clock output enable, control src0 and src2, 0 = enable. mode selected by smbus control register. default is src3. 25 srcc3/cr#_d i/o src clock/ src differential clock output enable, control src1 and src4, 0 = enable. mode selected by smbus control register. default is src3.. 26 v dd _src_io pwr 0.8v 27 srct4 out differential output clock 28 srcc4 out differential output clock 29 cpu_stop#/srcc5 i/o cpu stop, low = stop/ src clock. mode selected by pin6, src5_en. 30 pci_stop#/srct5 i/o pci stop, low = stop/ src clock. mode selected by pin6, src5_en. 31 v dd _src pwr 3.3v 32 srcc6 out differential output clock 33 srct6 out differential output clock 34 v ss _src gnd gnd 35 srcc7/cr#_e i/o src clock/ src differential clock output enable, control src6, 0 = enable. mode selected by smbus control register. default is src7. 36 srct7/cr#_f i/o src clock/ src differential clock output enable, control src8, 0 = enable. mode selected by smbus control register. default is src7. 37 v dd _src_io pwr 0.8v 38 srcc8/cpu_ itpc out src clock/cpu clock. mode selected by pin7. 39 srct8/cpu_ itpt out src clock/cpu clock. mode selected by pin7. 40 io_v out out v_io adjustment
commercial temperature range 4 idtcv174c programmable flexpc clock for p4 processor pin description, continued frequency selection fsc, b, a cpu src[7:0] pci usb dot ref 101 100 100 33.3 48 96 14.318 001 133 100 33.3 48 96 14.318 011 166 100 33.3 48 96 14.318 010 200 100 33.3 48 96 14.318 000 266 100 33.3 48 96 14.318 100 333 100 33.3 48 96 14.318 110 400 100 33.3 48 96 14.318 111 reserve 100 33.3 48 96 14.318 test mode selection (1) if test_sel sampled above 2v at ckpwrgd active low test_mode cpu src pci/f ref dot_96/dot_ssc usb 1 ref/n ref/n ref/n ref ref/n ref/n 0 hi-z hi-z hi-z hi-z hi-z hi-z note: 1. once test clock operation has been invoked, test_mode pin will select between the hi-z and ref/n, with v ih _fs and v il _fs threshoulds. pin # name type description 41 v dd _cpu_io pwr 0.8v 42 cpuc1 out differential output clock 43 cput1 out differential output clock 44 v ss _cpu gnd gnd 45 cpuc0 out differential output clock 46 cput0 out differential output clock 47 v dd _cpu pwr 3.3v 48 ckpwrgd/pd# in ckpwrgd power good, active low, used to latch fsa,b,c, itp_en, tme, and src5_en , active high. after, becomes power down, low active. 49 fs_b/testmode i n frequency select at ckpwrgd assertion. test mode selection, see test_mode selection table 50 v ss _ref gnd gnd 51 xtal_out out xtal out 52 xtal_in in xtal in 53 v dd _ref pwr 3.3v 54 ref/fs_c/testsel i/o 14.318mhz. frequency select at ckpwrgd assertion. selects test mode if pulled above 2v at ckpwrgd assertion. 55 sda i/o smbus clock 56 scl in smbus data
commercial temperature range idtcv174c programmable flexpc clock for p4 processor 5 index block write protocol bit # of bits from description 1 1 master start 2-9 8 master d2h 10 1 slave ack (acknowledge) 11-18 8 master register offset byte (starting byte) 19 1 slave ack (acknowledge) 20-27 8 master byte count, n (0 is not valid) 28 1 slave ack (acknowledge) 29-36 8 master first data byte (offset data byte) 37 1 slave ack (acknowledge) 38-45 8 master 2nd data byte 46 1 slave ack (acknowledge) : master nth data byte slave acknowledge master stop index block read protocol master can stop reading any time by issuing the stop bit without waiting until nth byte (byte count bit 30-37). bit # of bits from description 1 1 master start 2-9 8 master d2h 10 1 slave ack (acknowledge) 11-18 8 master register offset byte (starting byte) 19 1 slave ack (acknowledge) 20 1 master repeated start 21-28 8 master d3h 29 1 slave ack (acknowledge) 30-37 8 slave byte count, n (block read back of n bytes) 38 1 master ack (acknowledge) 39-46 8 slave first data byte (offset data byte) 47 1 master ack (acknowledge) 48-55 8 slave 2nd data byte ack (acknowledge) : master ack (acknowledge) slave nth data byte not acknowledge master stop symbol description min max unit v dda 3.3v core supply voltage 4.6 v v dd 3.3v logic input supply voltage gnd - 0.5 4.6 v t stg storage temperature ?65 +150 c t ambient ambient operating temperature 0 +70 c t case case temperature +115 c esd prot input esd protection 2000 v human body model absolute maximum ratings (1) note: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. sm protocol n resolution (mhz) % n = cpu = 100mhz 0.500000 0.5% 200 cpu = 133mhz 0.666667 0.5% 200 cpu = 166mhz 0.666667 0.4% 250 cpu = 200mhz 1.000000 0.5% 200 cpu = 266mhz 1.333333 0.5% 200 cpu = 333mhz 1.333333 0.4% 250 cpu = 400mhz 2.000000 0.5% 200 src = 100mhz 0.500000 0.5% 200 resolution
commercial temperature range 6 idtcv174c programmable flexpc clock for p4 processor pll#_cfb[3,2,1,0] comments 0000 pll3 disabled pll3 off, s rc1 = src_main 0001 100mhz 0.5% ssc stby pll3 on, src1 = src_main 0010 100mhz 0.5% ssc only src1 sourced from pll3 0011 100mhz 1.0% ssc only src1 sourced from pll3 0100 100mhz 1.5% ssc only src1 sourced from pll3 0101 100mhz 2.0% ssc only src1 sourced from pll3 0110 100mhz 2.5% ssc only src1 sourced from pll3 0111 reserved reserved 1000 1394a 3.3v only 1394a on se1 and se2 1001 1394a&b 3.3v only 1394a on se1, 1394b on se2 1010 1394b 3.3v only 1394b on se1 and se2 1011 27mhz, 3.3v only 27mhz on se1 and se2 1100 25mhz 3.3v only 25mhz on se1 and se2 1101 reserved reserved 1110 reserved reserved 1111 reserved reserved pll3 config table (1) note: 1. pll3 spread depend on byte4 bit0 and byte1 bit5, default -0.5%. 000 0.3v 001 0.4v 010 0.5v 011 0.6v 100 0.7v 101 0.8v 110 0.9v 111 1v io_vout [2:0] table ib1, ib0 cpu frequency 01 (n + 0.3333) * resolution 10 (n + 0.6666) * resolution 00, 11 n * resolution ib table id3,id2,id1,id0 comments 0000 ck505 56 pin tssop ck505 yc 0001 ck505 64 pin tssop ck505 yc 0010 48 pin qfn ck505 yc 0011 56 pin qfn ck505 yc 0100 64 pin qfn ck505 yc 0101 72 pin qfn ck505 yc 0110 48 pin ssop ck505 yc 0111 56 pin ssop ck505 yc 1000 reserved ck505 derivative (non yc) 1001 reserved 1010 reserved 1011 reserved 1100 reserved 1101 reserved 1110 reserved 1111 reserved device id table
commercial temperature range idtcv174c programmable flexpc clock for p4 processor 7 byte 2 bit output(s) affected description/function 0 1 type power on 7 ref output enable tristate enable rw 1 6 usb_48 output enable tristate enable rw 1 5 pcif5 output enable tristate enable rw 1 4 pci4 output enable tristate enable rw 1 3 pci3 output enable tristate enable rw 1 2 pci2 output enable tristate enable rw 1 1 pci1 output enable tristate enable rw 1 0 pci0 output enable tristate enable rw 1 control registers byte 0 bit output(s) affected description/function 0 1 type power on 7 fsc latched fsc r latched value 6 fsb latched fsb r latched value 5 fsa latched fsa r latched value 4 iamt_en iamt mode legacy mode enabled rw hw m1 setting (1) 3 reserved 0 2 src_sel src clock source pll1, pll3_cfg pll3, pll3_cfg rw 0 table applies table not applicable 1 sata_sel sata source src_main pll2 (2) rw 0 0 pd_restore smbus control registers setting power on default save register contents rw 1 after the power down notes: 1. sticky 1, can only be reset by power off. 2. 100mhz, no ssc. byte 1 bit output(s) affected description/function 0 1 type power on 7 src0_sel pin13/14 mode select src0 dot96 rw 0 6 pll1_ssc_dc ssc mode selection down spread center spread rw 0 5 pll3_ssc_dc ssc mode selection down spread center spread rw 0 4 pll3_cfb3 rw 0 3 pll3_cfb2 only valid if byte0 bit2 = 0 rw 0 2 pll3_cfb1 see pll3_cfb table, rw 0 1 pll3_cfb0 configure pin17, 18 output mode rw 1 0 pci pci select pll1 src, as byte0 bit2 rw 1 cpu 1. power on cpu frequency = 200mhz. resolution corresponding to 200mhz is 1.0 2. to change cpu frequency from 200mhz to 100mhz, divide 100 by 1.0- (100 / 1.0 = 100 [decimal] = 64 [hex]). 3. program byte 17 with 64h. cpu frequency changes from 200mhz to 100mhz. src 1. power on src frequency = 100mhz. 2. to change src frequency from 100mhz to 50mhz, divide 50 by 0.5 (50 / 0.5 = 100 [decimal] = 64 [hex]). 3. program byte 18 with 64h. src frequency changes from 100mhz to 50mhz. n-programming procedure
commercial temperature range 8 idtcv174c programmable flexpc clock for p4 processor byte 6 (1) bit output(s) affected description/function 0 1 type power on 7 cr#_e pin 35 mode selection, control src6 srcc7 mode cr#_e mode rw 0 6 cr#_f pin 36 mode selection, control src8 srct7 mode cr#_f mode rw 0 5 reserved rw 0 4 reserved rw 0 3 reserved rw 0 2 reserved rw 0 1 sscd_stp_crtl if set, sscd stop with pci_stop# free running stoppable rw 0 0 src_stp_crtl if set, srcs stop with pci_stop# free running stoppable rw 0 note: 1. stop - cput and srct stay high, cpuc and srcc stay low. bit output(s) affected description/function 0 1 type power on 7 reserved rw 1 6 reserved rw 1 5 reserved rw 1 4 src8/itp output enable tristate enabled rw 1 3 src7 output enable tristate enabled rw 1 2 src6 output enable tristate enabled rw 1 1 src5 output enable tristate enabled rw 1 0 src4 output enable tristate enabled rw 1 byte 3 byte 4 bit output(s) affected description/function 0 1 type power on 7 src3 output enable disabled enabled rw 1 6 sata/src2 output enable disabled enabled rw 1 5 src1 output enable disabled enabled rw 1 4 src0/dot96 output enable disabled enabled rw 1 3 cpu1 output enable disabled enabled rw 1 2 cpu0 output enable disabled enabled rw 1 1 pll1_ssc_on ssc enable disabled enabled rw 1 0 pll3_ssc_on ssc enable disabled enabled rw 1 byte 5 bit output(s) affected description/function 0 1 type power on 7 cr#_a pin1 mode selection pci0 mode cr#_a mode rw 0 6 cr#_a control cr#_a control selection src0 src2 rw 0 5 cr#_b pin3 mode selection pci1mode cr#_b mode rw 0 4 cr#_b control cr#_b control selection src1 (1) src4 rw 0 3 cr#_c pin24 mode selection srct3 mode cr#_c mode rw 0 2 cr#_c control cr#_c control selection src0 src2 rw 0 1 cr#_d pin25 mode selection srcc3 mode cr#_d mode rw 0 0 cr#_d control cr#_d control selection src1 src4 rw 0 note: 1. only when src1 is src clock.
commercial temperature range idtcv174c programmable flexpc clock for p4 processor 9 byte 7 bit output(s) affected description / function 0 1 type power on 7 revision id 0 6 revision id 0 5 revision id 0 4 revision id 0 3 vendor id 0 2 vendor id 1 1 vendor id 0 0 vendor id 1 bit output(s) affected description / function 0 1 type power on 7 device_id3 r 6 device_id2 see device id table r 5 device_id1 r 4 device_id0 r 3 rw 0 2 rw 0 1 se1_oe output enable disabled enabled rw 0 0 se2_oe output enable disabled enabled rw 0 byte 8 byte 9 bit output(s) affected description / function 0 1 type power on 7 pcif5 with pci_stop# free running free running stoppable rw 0 6 lte_strap over-clocking enable (n programming) normal no overclocking r 0 5 ref drive strength strength control 1x 2x rw 1 4 only valid when byte9 bit3 is 1 hi-z ref/n mode rw 0 3 test mode entry control normal operation test mode, controlled rw 0 by byte9 bit 4 2 io_vout2 rw 1 1 io_vout1 programmable io_v out voltage rw 0 0 io_vout0 rw 1 bytes 10 + 11 - reserved byte 12 - byte count - default 0x0d byte 13 bit output(s) affected description / function 0 1 type power on 7 48m strength control 1 1.2 rw 0 6 ref strength control 1 1.2 rw 0 5 pcif5 strength control 1 1.2 rw 0 4 pci4 strength control 1 1.2 rw 0 3 pci3 strength control 1 1.2 rw 0 2 pci2 strength control 1 1.2 rw 0 1 pci1 strength control 1 1.2 rw 0 0 pci0 strength control 1 1.2 rw 0
commercial temperature range 10 idtcv174c programmable flexpc clock for p4 processor byte 14 bit output(s) affected description / function 0 1 type power on 7 src skew selection 250ps 400ps rw 0 6 reserved rw 0 5 reserved rw 0 4 src3, 4, 5, 6 strength (output impedance) 17 ? 25 ? rw 0 3 src2, 7, 8 strength 17 ? 25 ? rw 0 2 cpu strength strength 17 ? 25 ? rw 0 1 src0/ dot strength strength 17 ? 25 ? rw 0 0 src1/ pll3clk strength strength 17 ? 25 ? rw 0 byte 16 bit output(s) affected description / function 0 1 type power on 7 wdeapd set byte15 bit7 = 1 after power down disabled enabled rw 0 to enable the watch dog after the power down 6 reserved rw 0 5 reserved rw 0 4 reserved rw 0 3 reserved rw 0 2 ib1 increment bit1, fine tune cpu frequnecy see ib table rw 0 1 ib0 increment bit0 see ib table rw 0 0 cpun8 rw fs latch byte 17 (pll1) bit output(s) affected description / function 0 1 type power on 7 cpun7 rw 6 cpun6 rw 5 cpun5 cpu frequency = n*resolution rw 4 cpun4 (see resolution table, rw fs latch 3 cpun3 n-programming procedure) rw 2 cpun2 rw 1 cpun1 rw 0 cpun0 rw byte 15, watch dog (1) bit output(s) affected description / function 0 1 type power on 7 watch dog enable watch dog alarm enable disabled enabled rw 0 6 watch dog select watch dog hard/soft alarm select hard alarm only hard and soft alarm rw 0 5 watch dog hard alarm status watch dog hard alarm status normal alarm r 4 watch dog soft alarm status watch dog soft alarm status normal alarm r 3 watch dog control watch dog time base control 290ms base 1160ms base rw 0 2 wd_1_ timer 2 watchdog_1_alarm timer rw 1 1 wd_1_ timer 1 default is 7*290ms rw 1 0 wd_1_ timer 0 rw 1 note: 1. hard alarm switch to hw fs frequency.
commercial temperature range idtcv174c programmable flexpc clock for p4 processor 11 bit output(s) affected description/ function 0 1 type power on 7 c pu m ode c ontrol will be reset to o during the h ard alarm c pu mode is based on h ardw are sfs c pu m ode is based on sfs rw 0 6sfsc rwlatch 5 sfsb rw latch 4 sfsa rw latch 3 n programming enable enable disable rw power on lte latch 2 src 1 source controlled by pll3_c fb[3:0] and by te0 bit2 pll2 rw 0 1 pc i source follow by te1 bit0 pll2 rw 0 0 reserv ed - - - - 0 byte 19, clock source selection, writen after stop bit byte 18 (pll3) bit output(s) affected description / function 0 1 type power on 7 pn 7 rw 6 pn 6 rw 5 pn 5 src frequency = n*resolution rw 4 pn 4 (see resolution table, rw 100mhz 3 pn 3 n-programming procedure) rw 2 pn 2 rw 1 pn 1 rw 0 pn 0 rw
commercial temperature range 12 idtcv174c programmable flexpc clock for p4 processor symbol parameter test conditions min. max. unit v dd _3.3 supply voltageoperating supply current 5 % 3.125 3.465 v v ih input high voltage (se) (1) 2v dd + 0.3 v v il input low voltage (se) (1) v ss - 0.3 0.8 v v ih _fs_test input high voltage (se) (2) 2v dd + 0.3 v v ih _fs_normal input high voltage (fs) (2) 0.7 1.5 v v il _fs_normal input low voltage (fs) (2) v ss - 0.3 0.35 v i il input leakagecurrent (3) 0 < v in < v dd ?5 +5 a v oh output high voltage (se) (4) i oh = ?1 ma 2.4 ? v v ol output low voltage (se) (4) i ol = 1 ma ? .4 v v dd _io low voltage differential 0.72 0.88 v c in input pin capacitance 1.5 5 pf c out output pin capacitance ? 6 pf i dd _cfg1_3.3v operating supply current, default configuration ? 250 ma i dd _cfg2_3.3v operating supply current, pll3 differential out ? 250 ma i dd _cfg3_3.3v operating supply current, pll3 single-ended out ? 250 ma i dd _io_o.8v differential io current, all outputs enabled 25 80 ma i dd _pwrdwn_3.3v power down supply current ? 1 ma i dd _pwrdwn_0.8v power down supply current ? 0.1 ma i dd _m1_3.3v mt mode supply current ? 25 ma i dd _m1_0/8v mt mode supply current ? 0.8 ma dc operating characteristics following conditions apply unless otherwise specified: operating condition: t a = 0c to +70c, supply voltage: v dd = 3.3v 5% notes: 1. all inputs referenced to 3.3v power suppply. 2. frequency select inputs which have tri-level input. 3. input leakage current does not include inputs with pull-up or pull-down resistors. 4. signal edge is required to be monotonic when transitioning through this region.
commercial temperature range idtcv174c programmable flexpc clock for p4 processor 13 symbol parameter test conditions min. typ. max. unit v high voltage high (2) statistical measurement on single-ended signal using 660 ? 850 mv v low voltage low (2) oscilloscope math function ?150 ? +150 v ovs max voltage (2) measurement on single-ended signal using absolute value ? ? 1150 mv v uds min voltage (2) ?300 ? ? v cross(abs) crossing voltage (abs) (2) 250 ? 550 mv d - v cross crossing voltage (var) (2) variation of crossing over all edges ? ? 140 mv ppm static error (2,3) see t period min. - max. values ? ? 0 ppm 400mhz nominal / -0.5% spread 2.4993 ? 2.5133 333.33mhz nominal / -0.5% spread 2.9991 ? 3.016 266.66mhz nominal / -0.5% spread 3.7489 ? 3.77 t period average period (3) 200mhz nominal / -0.5% spread 4.9985 ? 5.0266 ns 166.66mhz nominal / -0.5% spread 5.9982 ? 6.032 133.33mhz nominal / -0.5% spread 7.4978 ? 7.54 100mhz nominal / -0.5% spread 9.997 ? 10.0533 96mhz nominal 10.4135 ? 10.4198 400mhz nominal / -0.5% spread 2.4143 ? ? 333.33mhz nominal / -0.5% spread 2.9141 ? ? 266.66mhz nominal / -0.5% spread 3.6639 ? ? 200mhz nominal / -0.5% spread 4.9135 ? ? t absmin absolute min period (2,3) 166.66mhz nominal / -0.5% spread 5.9132 ? ? ns 133.33mhz nominal / -0.5% spread 7.4128 ? ? 100mhz nominal / -0.5% spread 9.912 ? ? 96mhz nominal 10.1635 ? ? t r rise time (2) v ol = 0.175v, v oh = 0.525v 175 ? 700 ps t f fall time (2) v ol = 0.175v, v oh = 0.525v 175 ? 700 ps d-t r rise time variation (2) ? ? 125 ps d-t f fall time variation (2) ? ? 125 ps d t3 duty cycle (2) measurement from differential waveform 45 ? 55 % electrical characteristics - cpu, src, and dot96 0.7 differential pair (1) following conditions apply unless otherwise specified: operating condition: t a = 0c to +70c, supply voltage: v dd = 3.3v 5%; c l = 2pf notes: 1. src clock outputs run only at 100mhz. 2. this parameter is guaranteed by design, but not 100% production tested. 3. all long term accuracy and clock period specifications are guaranteed with the assumption that the ref output is at 14.31818m hz.
commercial temperature range 14 idtcv174c programmable flexpc clock for p4 processor symbol parameter test conditions min. typ. max. unit ppm static error (1,2) see tperiod min. - max. values ? ? 0 ppm t period clock period (2) 33.33mhz output nominal 29.991 ? 30.009 ns 33.33mhz output spread 29.991 ? 30.1598 v oh output high voltage i oh = -1ma 2.4 ? ? v v ol output low voltage i ol = 1ma ? ? 0.55 v i oh output high current v oh at min. = 1v -33 ? ? ma v oh at max. = 3.135v ? ? -33 i ol output low current v ol at min. = 1.95v 30 ? ? ma v ol at max. = 0.4v ? ? 38 edge rate (1) rising edge rate 1 ? 4 v/ns edge rate (1) falling edge rate 1 ? 4 v/ns t r1 rise time (1) v ol = 0.8v, v oh = 2v 0.3 ? 1.2 ns t f1 fall time (1) v ol = 0.8v, v oh = 2v 0.3 ? 1.2 ns d t1 duty cycle (1) v t = 1.5v 45 ? 55 % t sk1 skew (1) v t = 1.5v ? ? 250 ps t jcyc - cyc jitter, cycle to cycle (1) v t = 1.5v ? ? 500 ps electrical characteristics - pciclk / pciclk_f following conditions apply unless otherwise specified: operating condition: t a = 0c to +70c, supply voltage: v dd = 3.3v 5%; c l = 10 - 30pf notes: 1. this parameter is guaranteed by design, but not 100% production tested. 2. all long term accuracy and clock period specifications are guaranteed with the assumption that the ref output is at 14.31818m hz. electrical characteristics - cpu, src, and dot96 0.7 current mode differential pair, continued (1) following conditions apply unless otherwise specified: operating condition: t a = 0c to +70c, supply voltage: v dd = 3.3v 5%; c l = 2pf symbol parameter test conditions min. typ. max. unit skew, cpu[1:0] (2) ? ? 100 t sk 3 skew, cpu2 (2) v t = 50% ? ? 250 ps skew, src (2) ? ? 250 jitter, cycle to cycle, cpu[1:0] (2) ?? 85 t jcyc - cyc jitter, cycle to cycle, cpu2 (2) measurement from differential waveform ? ? 100 ps jitter, cycle to cycle, src (2) ? ? 125 jitter, cycle to cycle, dot96 (2) ? ? 250 notes: 1. src clock outputs run only at 100mhz. 2. this parameter is guaranteed by design, but not 100% production tested.
commercial temperature range idtcv174c programmable flexpc clock for p4 processor 15 symbol parameter test conditions min. typ. max. unit ppm static error (1,2) see tperiod min. - max. values ? ? 0 ppm t period clock period (2) 48mhz output nominal 20.8257 ? 20.834 ns v oh output high voltage i oh = -1ma 2.4 ? ? v v ol output low voltage i ol = 1ma ? ? 0.55 v i oh output high current v oh at min. = 1v -29 ? ? ma v oh at max. = 3.135v ? ? -23 i ol output low current v ol at min. = 1.95v 29 ? ? ma v ol at max. = 0.4v ? ? 27 edge rate (1) rising edge rate 1 ? 2 v/ns edge rate (1) falling edge rate 1 ? 2 v/ns t r1 rise time (1) v ol = 0.8v, v oh = 2v 0.5 ? 1.2 ns t f1 fall time (1) v ol = 0.8v, v oh = 2v 0.5 ? 1.2 ns d t1 duty cycle (1) v t = 1.5v 45 ? 55 % t jcyc - cyc jitter, cycle to cycle ? ? 350 ps electrical characteristics, 48mhz, usb following conditions apply unless otherwise specified: operating condition: t a = 0c to +70c, supply voltage: v dd = 3.3v 5%; c l = 10 - 20pf notes: 1. this parameter is guaranteed by design, but not 100% production tested. 2. all long term accuracy and clock period specifications are guaranteed with the assumption that the ref output is at 14.31818m hz. symbol parameter test conditions min. typ. max. unit ppm long accuracy (1) see tperiod min. - max. values ? ? 0 ppm t period clock period 14.318mhz output nominal 69.827 ? 69.855 ns v oh output high voltage (1) i oh = -1ma 2.4 ? ? v v ol output low voltage (1) i ol = 1ma ? ? 0.4 v i oh output high current v oh at min. = 1v -33 ? ? ma v oh at max. = 3.135v ? ? -33 i ol output low current v ol at min. = 1.95v 30 ? ? ma v ol at max. = 0.4v ? ? 38 edge rate (1) rising edge rate 1 ? 4 v/ns edge rate (1) falling edge rate 1 ? 4 v/ns t r 1 rise time (1) v ol = 0.8v, v oh = 2v 0.3 ? 1.2 ns t f 1 fall time (1) v ol = 0.8v, v oh = 2v 0.3 ? 1.2 ns d t1 duty cycle (1) v t = 1.5v 45 ? 55 % t jcyc - cyc jitter, cycle to cycle (1) v t = 1.5v ? ? 1000 ps electrical characteristics - ref-14.318mhz following conditions apply unless otherwise specified: operating condition: t a = 0c to +70c, supply voltage: v dd = 3.3v 5%; c l = 10 - 20pf note: 1. this parameter is guaranteed by design, but not 100% production tested.
commercial temperature range 16 idtcv174c programmable flexpc clock for p4 processor symbol parameter min. max. unit t stable all clock stabilization from power-up ? <1.8 ns t drive _src src output driven after pci_stop# de-assertion ? 15 ns t drive _pci pci output driven after pci_stop# de-assertion ? 15 us t drive _cr# src output driven after cr# de-assertion ? 15 ns t drive _p wrdwn differential output enable after p wrdwn de-assertion ? 300 ns t rise _control_sig rise time for all control inputs (lvttl 20-80%) ? 10 us t fall _control_sig fall time for all control inputs (lvttl 20-80%) ? 10 ns misc. ac timing requirements
commercial temperature range idtcv174c programmable flexpc clock for p4 processor 17 pci_stop# pcif5 33mhz pci[4:0] 33mhz src 100mhz src# 100mhz t su pci_stop# pcif5 33mhz pci[4:0] 33mhz src 100mhz src# 100mhz t su t drive_src pci stop functionality pci_stop# src src# pci 1 normal normal 33mhz 0 high low low pci_stop# assertion (transition from ?1? to ?0?) pci_stop# - de-assertion (transition from '0' to '1')
commercial temperature range 18 idtcv174c programmable flexpc clock for p4 processor cpu_stop# cpu cpu# cpu_stop# cpu cpu# cpu internal t drive _cpu_stop 10ns > 200mv cpu stop functionality the cpu_stop# signal is an active low input controlling the cpu outputs. this signal can be asserted asynchronously. cpu_stop# assertion (transition from ?1? to ?0?) asserting cpu_stop# pin stops all cpu outputs that are set to be stoppable after their next transition. when the smbus cpu_stop tri-state bit corresponding to the cpu output of interest is programmed to a ?0?, cpu output will stop cpu_true = high and cpu_complement = low. when the s mbus cpu_stop# tri-state bit corresponding to the cpu output of interest is programmed to a ?1?, cpu outputs will be tri-stated. cpu_stop# - de-assertion (transition from ?0? to ?1?) with the de-assertion of cpu_stop# all stopped cpu outputs will resume without a glitch. the maximum latency from the de-assert ion to active outputs is two to six cpu clock periods. if the control register tristate bit corresponding to the output of interest is programmed to ?1?, then the stopped cpu outputs will be driven high within 10ns of cpu_stop# de-assertion to a voltage greater than 200mv. cpu_stop# cpu cpu# 1 normal normal 0 high low
commercial temperature range idtcv174c programmable flexpc clock for p4 processor 19 pd# cpu 133mhz cpu# 133mhz src 100mhz src# 100mhz usb 48mhz pci 33mhz ref 14.31818 pd# assertion pd# de-assertion pd# cpu 133mhz cpu# 133mhz src 100mhz src# 100mhz usb 48mhz pci 33mhz ref 14.31818 t stable <1.8ms
commercial temperature range 20 idtcv174c programmable flexpc clock for p4 processor corporate headquarters for sales: for tech support: 6024 silver creek valley road 800-345-7015 or 408-284-8200 logichelp@idt.com san jose, ca 95138 fax: 408-284-2775 www.idt.com ordering information idtcv device type package grade xxx xx x commercial temperature range (0c to +70c) blank pag 174c thin shrink small outline package - green programmable flexpc clock for p4 processor pvg shrink small outline package - green
commercial temperature range idtcv174c programmable flexpc clock for p4 processor 21 may 22, 2006 final release.

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